1. Field of the Invention
This invention relates to electronic circuits, and in particular to a concurrent time and voltage matrix non-binary encoding circuit capable of transmitting and receiving a large number of multiple binary signals on a single physical I/O pin. By incorporating novel concurrent time and voltage encoding techniques, the present invention can N:1 encode N binary input signals onto a single non-binary data bit stream, and can 1:N decode the single non-binary data bit stream into N binary output signals.
2. Description of the Prior Art
Multiplexing circuits for encoding and decoding multiple binary signals are well known. In a conventional multiplexing scheme, binary signals are encoded and decoded by one of two methods. The first method, time-based multiplexing incorporates timedependent encoding of N bits of data into one or more discrete time slots. Each time slot represents either one clocking period, wherein the encoded output bit rate equals the clocking frequency, or less than one clocking period if multistage time multiplexers are used. Multistage multiplexing requires a pair of data bits to be multiplexed at each stage. If four bits of data are to be multiplexed, two stages are needed with a special time slot for each stage. Such a system is described in the article entitled "A 4:1 Time-Division Multiplexer IC for Bit Rates up to 6 Gbit/s Based on a Standard Bipolar Technology" published in the Journal of Solid-State Circuits, Vol, SC-21, No. 5, October 1986.
The second method, voltage-based multiplexing, is capable of encoding N bits of data into one or more discrete voltage levels during a set time period. Conventional voltage multiplexing circuits require precharging of the output line and switching the pre-charged line to multiple logic levels corresponding to binary input states. Such a system is described in an article by Singh entitled "Four Valued Buses for Clocked CMOS VLSI Systems" published by the IEEE in 1987. The time required to pre-charge the output line reduces the encoding time period, and thus, the multiplexing speed of the conventional voltage multiplexing circuit.
Using either a time or voltage multiplexing method allows only a limited number of bits of data to be transmitted and received on a single I/O pin. However, with recent increases in device density within an integrated circuit (IC), there is a need for greater number of bits of data to be multiplexed within a given time cycle. One of the major limitations of VLSI IC technology is the limited availability of I/O signal pads. I/O pad density on a VLSI IC or chip is directly proportional to the chip's peripheral dimensions. Although device density has increased drastically in recent years, I/O pad density has remained relatively constant. This causes most large scale digital designs to be I/O-constrained. Typically, a much larger number of I/O pads than are available are needed to effectively utilize the increased gate density. In order to effectively utilize the increase in device density, it is imperative that multiplexing schemes use the limited number of I/O pads to transmit as many binary bits of data as possible.
Conventional multiplexing techniques are unable to transmit large numbers of binary bits of data on a limited number of I/O pads. Typical time-multiplexing techniques can encode N bits of data during one clocking cycle. N is generally limited to one bit if multistage time multiplexer circuits are not used. If two stage time multiplexers are used, N can be extended to two bits. Even with two bits of encoded data per clocking cycle, the number of virtual I/O pins is far below what is needed to keep pace with current device densities. When typical voltage-multiplexing techniques are used only N bits, using 2**N discrete output voltages, can be encoded per time slot. Furthermore, in some instances, depending on the chosen technology, conventional voltagemultiplexing circuitry requires that the output lines be pre-charged prior to logic level shifting. See the above referenced article by Singh. The time required to precharge will limit the number of clocking cycles within a given time period. In turn, this would reduce the encoded data output frequency. Because the encoded data output frequency is so slow, the number of binary input signals that can be multiplexed within a given time frame is severely limited.